An Analytical Yield Model for Zero- $V_{\mathrm {GS}}$ -Load Thin-Film Transistor Logic Circuits

This letter presents an analytical circuit yield model for zero-V_GS-load thin-film transistor (TFT) logic circuits, which describes the circuit yield as a function of the circuit complexity, threshold voltage dispersion of TFTs, and circuit design parameters. By comparing the calculation result through the model with that by Monte Carlo statistical circuit simulations, the model is proved to be capable of providing a simple and effective way to predict the yield of a given zero-V_GS-load TFT circuit design, and is thus applicable for TFT performance evaluation or device and process optimization.