3-Gbit/s, 16-channel GaAs multiplexer and demultiplexer LSIs

A 16-channel multiplexer and demultiplexer LSI chip set has been designed, fabricated, and tested. A maximum operating speed of 3 Gb/s and a low power consumption of 2.0 W were realized. Using these ICs, the required mounting space was reduced by 1/70 and power consumption to 1/5 that of conventional discrete medium-scale integrated circuits. A high transconductance was obtained by using 1- mu m-long tungsten-silicide gate MESFETs. The transconductance was 270 mS/mm for a threshold voltage of -0.20 V at a gate bias of 0.6 V, and 230 mS/mm for a threshold voltage of -0.70 V at a gate bias of 0 V. A 5-20- mu m logic gate width was adopted to obtain wideband operation and lower power consumption. These optimizations were performed by computer simulation using the modified SPICE model.<>