Power, delay and noise margin comparison of binary and quaternary SRAM

The explosive growth of semiconductor industry over a decade have been driven by rapid scaling of complementary metal-oxide-semiconductor (CMOS) technology. Multiple-valued logic allows the reduction of the required number of signals in the circuit, so can be effectively used to reduce the impact of interconnections [12]. In addition to the reduction in interconnections, multiple-valued logic also offers a possibility of increasing the functional complexity, producing circuits that have performance comparable to the binary circuits. Memory application is an area where the multi-valued approach has been successfully used to design commercial integrated circuits. Memories are designed with objective to reduce area, while maintaining proper timing characteristics. This paper presents a comparative study of delay and power consumption of binary and quaternary circuit implementations of SRAM. Larger number of logic functions can be accommodate in quaternary circuits decreasing the number of data interconnect lines and processing components and logic circuits can represent numbers with fewer bits than binary. Static Noise Margin (SNM) is the most important parameter for memory design, affecting both read and write margin [8]. Both cell ratio and pull-up ratio are important parameters because these are the only parameters in the hand of the design engineer, static noise margin of the SRAM cell depends on the cell ratio (CR), supply voltage and also pull up ratio [8]. We have also found bit rate of both circuits for comparative study.