0.75-V four-quadrant current multiplier using floating gate-MOS transistors

This paper presents a new ultra-low-voltage current-mode four-quadrant analog multiplier. A floating-gate technique is used to provide operating at a supply voltage of 0.75 V for the proposed circuit. PSPICE simulators using 0.18 μm TSMC CMOS process are used to show the workability of the multiplier. Simulation results show that the circuit has a linearity error of 1.5 % for the input current 8 μA, total harmonic distortion of 0.96 % for the input current 8 μA_peak and quiescent power consumption of 19.9 μW.