Design of high performance 16 bit multiplier using vedic multiplication algorithm with McCMOS technique

This paper contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel CMOS (Mc CMOS) technology. We have designed 16 bit Vedic multiplier using McCMOS technology and used 65nm and 45nm node technology and comparative simulation results that indicates the performance of the circuit. Vedic mathematics is a ancient Indian mathematics is very useful for doing tedious and cumbersome mathematical calculation at a very fast rate. The Vedic Urdhva-Tiryakbhyam multiplier is approximately 10 times faster performance than the conventional multiplier architecture. Thorough simulations of 16 × 16 digital Vedic multiplier we are using McCMOS Technology which show the Power Delay Product (PDP) is reduced by approximately 75 % compared to the conventional multiplier design. The simulations have been carried out in cadence-spice simulator with 1V power supply. This technique will be very useful for designing low leakage high speed ALU unit.