New improved low power and high SNM single metal SRAM in 32 nm technology

The driving forces behind the need for the development of different SRAM designs are power dissipation and delay reduction along with improvement of cell stability. SRAM cell stability assessment is traditionally based on static criteria of data stability calculated through Static Noise Margin. This paper focuses on comparison of two SRAM designs by calculation of power consumption; write delay and stability based on SNM for frequencies up to 5 GHz. The new improved single metal SRAM design is better than conventional double metal SRAM design as- on chip area utilization is reduced by 8.7%, write 1 delay by 4.26% and write 0 delay by 3.15%. Also, single metal SRAM design is slightly more stable because SNM is improved marginally from 124.16 mV to 124.36 mV which is nearly 0.16%.