Statistical process modelling for 32nm high-K/metal gate PMOS device

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO
₂
/TiSi
₂
PMOS device is presented; replacing the conventional SiO
₂
dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (V
_TH
) and leakage current (I
_OFF
). The simulation result shows that the optimal value of V
_TH
and I
_OFF
which are 0.1030075V and 3.4264075×10
^-12
A/um respectively are well within ITRS prediction.