Design and embodiment of larger quaternary multiplexer and demultiplexer

In this work, the implementation of the novel quaternary algebra over the larger quaternary multiplexer and demuliplexer are performed. Both arbitrary multiplexer and demultiplexer are designed using the larger quaternary encoders and decoders respectively. This design validates the quaternary algebra to perform in building larger arbitrary logic blocks using different logic blocks with same principle. The design complexity has been compared with truth table and mathematical formulation under quaternary algebra and found perfect agreement with it.