Implementation of area and energy efficient full adder cell

This paper presents a low power full adder cell designed with transmission gate and pass-transistor logic styles that lead to have a reduced area, power and delay. We compared 28T conventional CMOS full-adders to 14T and 16T full adder cell, in terms of speed, power consumption and area. All the full-adders were designed with a 0.25um CMOS technology, and were tested using a tannerv13.0. After simulating CMOS and pass transistors based full adder, compared the average power consumption. 16T based Full adder consumed 98% less power compared to 28T conventional CMOS full adder.