Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications

A continuous-time low-pass ΔΣ ADC equipped with design techniques to provide robustness against saturation due to blockers is presented. An integrated low pass blocker filter that reduces the most critical adjacent/alternate channel blockers by 7/11 dB, respectively is implemented at the input of the ADC. The blocker filter is power efficient, highly linear and its noise is shaped out of signal band. Measurement results show that the proposed ADC implemented in a 90-nm digital CMOS process achieves 69 dB dynamic range over a 20 MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is −12.5 dBFS in the presence of a −12 dBFS in-band signal while the conventional modulator becomes unstable for −23.5 dBFS blocker power. The proposed integrated blocker filter is non-invasive, low power (1.4mW) and does not degrade the stability of the ΔΣ loop.