Digital hardware implementation of an active disturbance rejection controller for a highly dynamic parallel orientation manipulator

This paper details the development of a tracking controller for a highly dynamic parallel orientation manipulator that is capable of achieving high angular acceleration. The adopted control algorithm is derived from the active disturbance rejection control (ADRC) technology. The ADRC algorithm must be evaluated on the control hardware at a frequency consistent with the dynamics of the system without creating any inter-channel latency for a successful implementation. In this regard, the field programmable gate array (FPGA) is preferred because of its superior speed and parallelism. While there is a clear demand for FPGA controllers in the military and the aerospace domain because of the improved SWaP (size, weight, and power) capabilities, the literature provides a few examples of such controllers that mostly employ expensive high logic density FPGA chips. In contrast, this paper describes how an advanced controller can be efficiently prototyped on a relatively low-cost, low logic density FPGA hardware. The controller was tested in a co-simulation approach (wherein the digital implementation of the control algorithm and the dynamics of the manipulator are simulated together) to ensure a robust FPGA implementation. In addition, a hardware evaluation was also conducted using a linear voice coil actuator under varying inertial loads. Experimental results obtained from the simulation study and hardware testing confirm the robust performance of the designed controller.