VLSI architecture design for particle filtering in real-time

Particle Filter is an algorithm that provides system state estimation even for non-linear and non-gaussian systems. For applications that require a large number of particles, real time constraint is hard to accomplish since the algorithm is computationally expensive and the resampling step becomes a bottleneck. In this work, a VLSI architecture for particle filtering in real time is presented. The proposed design implements a fraction of the processing using piecewise linear functions and allocates them as global resources. In this way, a large number of processing elements (PE) working in parallel can be instantiated in the design. An example based on a range-only localization using Radio-Frequency identification (RFID) tags is developed to illustrate the approach. The received signal strength indicator (RSSI) is used to estimate the distance between transmitter and receiver. A VHDL RTL model of the processing data flow is implemented and compared to Matlab simulations showing similar results.