Modeling for reliability of ultra thin chips in a system in package

In this paper, ultrathin silicon chip failure mechanism and reliability performance of a system in package (SIP) package are investigated. Advanced finite element analysis (FEA) modeling is carried out to simulate die stress and delamination in the temperature cycling test. Parametric models with different ultrathin die thicknesses, different delamination areas and different bond wire positions are simulated. Temperature cycling modeling results have shown that the thinner die has lower tensile stress than the thicker die. Delamination increases die tensile stress in temperature cycling test. Larger delamination areas in the package induce higher die tensile stress. Comparing with three different delamination models, the model without delamination in the whole package induces lowest die tensile stress, the model with the largest delamination areas at die top surface, aluminum bond wire and lead frame DAP induces the highest die tensile stress. Finally, the modeling results disclose that the bond wire at different position has very limited impact on die stress during temperature cycling test.