A resilient 3-D stacked multicore processor fabricated using die-level 3-D integration and backside TSV technologies

A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.