ELK delaminate improvement methodology on Cu pillar interconnect BOP structure

During last couple years, the market of IC package have successful to implement Cu Pillar Flip Chip Technology as a mainstream of high density flip chip solution in each of portable markets(mobile phone, tablet & lots of portable entertainment solution). Moreover, concerning about high end product application which required 10*10mm above die area on larger flip chip ball grid array product, the substrate and bump dimension design will be an important factor to release ELK stress during huge CTE mis-match between silicon and organic substrate. After reviewed the product market trend of CuBOP package (Cu pillar bump attach on bump on pad substrate structure), interconnection methodology have stayed on a perfect position to serve lots of high end zone on networking, graphic and specific ASIC devices by benefit of high density (compared with solder bump) bump layout design. Compared with solder bump structure, Cu pillar bump owned better electron migration performance. In order to well define optimun construction while utilizing Cu FC Package on BOP substrate structure, the paper plan to align the stress simulation index & failed event point of view to define bump dimension and solder mask resist opening (SRO) relationship for future advance, high end product and large die size implementation. The analysis will utilize simulation methodology & popular reliability testing (Temperature Cycle Test, High Temperature, unbias HAST) result as a ranking for certain ratio definition between UBM dimension of bump design and SRO of substrate design. Based on stress simulation theoretical demonstration and actual practice result to find out that ELK wafer structure qualification index for real product application.