Session based core test scheduling for minimizing the testing time of 3D SOC

Three dimensional (3D) VLSI integration based on through-Silicon-Via (TSV) is an emerging technology. It provides heterogeneous integration, higher performance, bandwidth, and lower power consumption. However, 3D-IC suffers from several challenges. The objective of this paper is to design the test access mechanism (TAM) architecture and test scheduling of different modules of an system-on-chip (SOC) such that the overall test time of that SOC gets reduced. In this paper we have used a session based heuristic approach to solve this problem. Experimental results have been tested on different ITC'02 benchmark SOCs that shows promising results for different TAM width allocation.