Stacked gate dielectrics with TaO for future CMOS technologies

Advances in lithography and thinner SiO/sub 2/ gate oxides have enabled the scaling of MOS (metal-oxide-semiconductor) technologies to sub-0.25 μm feature size. High dielectric constant materials, such as Ta/sub 2/O/sub 5/, have been suggested as a substitute for SiO/sub 2/ as the gate material beyond t/sub ox/=25 Å. However, the Si-Ta/sub 2/O/sub 5/ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. We present a solution to these issues through the synthesis of a SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/ stacked dielectric. The fabricated transistors exhibit excellent I-V characteristics.