The application of through silicon vias (or TSVs) for high power and temperature devices

Miniaturization and higher functionality have been and continue to be serious pursuits of the electronics industry. In relation to the miniaturization of package size, the 3D integration of devices using through silicon vias (or TSVs) is currently being researched extensively. 2.5D integration with a passive interposer is currently being researched as a step toward achieving the goal of complete 3D integration. This paper analyzes the packaging industry's transition from 2D to 3D integration of packages. Literature focused on manufacturability, materials of interest, geometrical dimensions, market trends, and customer focus is discussed in detail. The utilization of TSV packages in high power and high temperature products is the research area still to be explored. Hence, existing simulation data is extrapolated to high power die dimensions to analyze the effect of package dimensions on the thermo-mechanical behavior of TSV power die. Furthermore, a basic thermo-mechanical model of a Cu-filled TSV passive interposer is studied under high power and high temperature field conditions. Multiple cases are simulated to study the effect of TSV dimensions and material properties on the thermo-mechanical behavior of power packages. The current limitations of TSVs in high power application s ar e stated based on the results.