A 2.4 GHz fast settling wake-up receiver frontend

This paper proposes the design of an integrated fast settling analog frontend for application in wireless wake-up receivers. The chip includes a low noise amplifier with matching transformer and integrated balun, a multi-hyperbolic tangent gilbert cell mixer with Sallen-Key filter, a limiting amplifier and a LC-cross coupled digital-controlled oscillator. The chain exhibits a measured conversion gain of 29 dB while only consuming an overall current of 3.3mA in its on-mode from a 2.5V supply. The measured input return loss is -19 dB at 2.4 GHz with a corresponding double sideband noise figure of 7.6 dB at an intermediate frequency of 51 MHz. The measured input referred 1 dB-compression point is at -44 dBm. All circuits enable on/off switching which allows operation within on-times of 200 ns. The component chain is optimized to settle in less than 60 ns until the output obtains -1 dB of its steady state amplitude. The proposed chip is fabricated in IHP 130 nm-SiGe-BiCMOS process.