InGaAs Double-gate fin-sidewall MOSFET

InGaAs Double-gate MOSFETs with fins as narrow as 12 nm we re fabricated using precision dry etching and digital etch. The primary goal is to use the subthreshold characteristics of long-channel devices to characterize the interface of etched InGaAs fin sidewalls. We have investigated the impact of forming gas anneal, high-K oxide and number of digital etch cycles following RIE. Our results indicate a minimum interface state density (D
it
) of ∼ 3×10
¹²
cm
⁻²
eV
⁻¹
obtained in fin sidewalls with Al
2
O
3
and HfO
2
oxides after 4 cycles of dig ital etch. This is equivalent to results reported on planar devices and bodes well for future Trigate MOSFETs that will not require a barrier semiconductor covering the sidewalls.