A novel high-speed 4-bit carry generator with a new structure for arithmetic operations

A new high speed 4-bit carry generator is proposed in this paper. A new structure has been introduced to reduce the delay from inputs to the outputs. Also this structure utilizes less number of transistors and it occupies smaller area size. Proposed structure has been simulated by HSPICE software in a typical 0.18 um CMOS technology and results show that there is a 500ps delay from inputs to output.