A novel fast glitchless 7-3 counter with a new structure

This paper discusses about the design of a novel fast 7-3 counter for CMOS low power, high speed multiplier. In order to reduce delay and increase the speed, some changes have been made in the structure of the counters. Also the occupied area by the counter is decreased because of the less number of transistors. The delay of the proposed structure is 185ps which is simulated by HSPICE using TSMC 0.18μm CMOS technology.