Efficient VHDL implementation of symbol synchronization for software radio based on FPGA

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed.