High performance and low cost implementation of Fast Fourier Transform algorithm based on Hardware Software co-design

The paper presents a high performance implementation of Fast Fourier Transform (FFT) algorithm using the notion of Hardware Software Partitioning. The co-design methodology was used to achieve higher system performance and design flexibility. The algorithm was originally implemented on a microcontroller (Atmegal6) but suffered from high execution delay. A low cost reconfigurable device like Spartan-3E Field Programmable Gate Array (FPGA) was then used to overcome this shortcoming, but the algorithm failed to be implemented on it, due to limited number of configurable logic blocks available within the capacity of the FPGA. Finally, a novel architecture has been realized based on hardware software partition with respect to implementation on microcontroller and FPGA together, such that the two devices communicate with each other, run synergistically and ensure optimality in power, delay and area. Also, a comparative study of the power dissipation, execution delay, area of implementing FFT on the different architectures: first, completely sequential (software), second, completely parallel, i.e. hardware (using FPGA) and third based on Hardware Software Co-design is performed. The power consumption of the co-design has been found to be 0.072W at a supply voltage 3.3V.