Soft error rate comparison of various hardened and non-hardened flip-flops at 28-nm node

For flip-flop designs fabricated at advanced technology nodes, soft errors are expected to contribute significantly to the overall failure-in-time rates for electronic systems. Since the soft error rates are design and layout dependent, it is important to evaluate different flip-flop designs used in an electronic system. Alpha-particle, high-energy proton, neutron, and heavy-ion experimental results of 30 different flip-flop designed and manufactured in a 28-nm bulk CMOS process are presented in this paper. The results show the spectrum of soft error rates a system-level designer may see for hardened and non-hardened flip-flops at the 28-nm bulk CMOS technology node.