Positive bias instability in gate-first and gate-last InGaAs channel n-MOSFETs

Instability under positive bias stress in the InGaAs channel n-MOSFETs with gate last Al2O3 and gate-first ZrO2/Al2O3 process flows is investigated. It is determined that the threshold voltage shift (ΔVT) during stress is primarily caused by a recoverable electron trapping at the pre-existing defects located predominantly in the Al2O3 interfacial layer (IL). Generation of new electron trapping defects is found to occur in the dielectric region adjacent to the substrate, while trap generation in the high-k bulk is negligible.