Asynchronous 8-bit processor mapped into an FPGA device

Asynchronous digital design paradigm promises benefits over current synchronous design, in power reduction, speed increase and lower Electro-Magnetic Interference (EMI). These are special characteristics that enable longer battery life and higher IP core integration. This paper describes the design and implementation of an 8-bit asynchronous processor mapped into FPGA devices, described in VHDL language, with a minimalist, novel architecture and a simple but complete arithmetic, logic, shifter and program flow instruction set. The aim of this development is to be a demonstration of mapping complex asynchronous circuits in commercial FPGA devices as a way to get acquainted, understand the capability and applicability of the technology. For demonstration, this processor has been carried out into the Xilinx Spartan-6 XC6SLX9 FPGA and each of the constitutive modules into the Xilinx CoolRunner-II CPLD family devices. The Authors believe that it is possible to be carried out in many other FPGA device families, with minor changes in the asynchronous latch instantiation and User Constraint Files.