Optimized packet pre-filtering for analysis of IP traffic on high-speed networks

In this paper an efficient FPGA implementation of a packet pre-filtering algorithm based on Bloom filter is presented. In high speed link the traffic classification involves a very large amount of data per each packet processed (header and payload analysis). This leads to use hardware with high computational power and very expensive, in order to support requirement of real-time classification. Our system, reducing the data flow sent to the classifier allows a real-time classification with reduced hardware resources.