A 155 GHz 20 Gbit/s QPSK transceiver in 45nm CMOS

This paper presents a 155 GHz 20 Gbit/s quadrature phase-shift-keying (QPSK) transceiver front-end with modulator, demodulator, LO chain and an option for external LO feed. The transceiver can achieve a bit error rate (BER) <; 10^-12 for an 19 Gbit/s 2³¹-1 pseudorandom binary sequence data at a received power of -20 dBm. The size of the chip is 2.8×1.4 mm² and consumes 345 mW with the on-chip LO (290 mW without the on-chip LO). To our knowledge, this is the first demonstration of a single-chip QPSK transceiver in CMOS at frequencies above 100 GHz.