An 8-bit 100-GS/s distributed DAC in 28-nm CMOS

An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS is presented. The ENOB and SFDR ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from DC up to 24.9 GHz at 100 GS/s. The -3dB bandwidth is larger than 10 GHz. The 100 GS/s DAC is composed of two 50 GS/s time-interleaved sub-DACs and is operated from two 25 GHz clock signals with a phase shift of 90°. Due to this structure, the output frequency roll-off is comparable to a 50 GS/s DAC while the output frequency image rejection is comparable to a 100 GS/s DAC, easing the output frequency band utilization. With 1-kbyte on-chip memory the DAC can convert 1k symbols cyclically, which is sufficient for characterizing the DAC performance. The DAC consumes 2.5 W from a 1.1V/1.5V/2V power supply. The area of the test chip is 1.5mm².