Generation and validation of multioperand carry save adders from the web

Many arithmetic circuits utilize multioperand addition, usually using carry-save adders (CSA) trees. Automatic generation of custom VHDL models for these CSA trees, allows the designer to perform a time efficient design space exploration. Although, the CSA trees are heavily utilized in modern digital circuits, there is no tool, accessible from the web, to generate the HDL description of such multioperand designs. To the best of our knowledge, our novel tool is the first one to automate the design of optimized CSA trees and simultaneously provide custom testbenches to verify their correctness. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 724 Mhz.