A 24 GHz low power low phase noise dual-mode phase locked loop frequency synthesizer for 60 GHz applications

This paper presents a dual-mode PLL synthesizer used in 60 GHz transceiver supporting both IEEE 802.11ad and IEEE 802.15.3c standards with low power consumption and low phase noise. Fabricated in commercial 0.18 μm SiGe BiCMOS process and operated with a single 1.8 V supply, the PLL synthesizer provides output frequencies from 22.5 GHz to 26.23 GHz with phase noise better than -99.5 dBc/Hz at 1 MHz offset in both the integer and fractional modes of operation. The PLL synthesizer consumes low power of only 42 mW and occupies an area of 1.7 mm × 0.8 mm.