Dynamic feedback and biasing for a linear CMOS power amplifier with envelope tracking

This paper presents a fully integrated CMOS power amplifier (PA) with a dynamic feedback and gate biasing. The two dynamic circuits improve the linearity and efficiency of the stand-alone PA and ET PA. The proposed CMOS ET PA including the dynamic control circuits is fabricated using 0.18-μm CMOS process. For a long-term evolution (LTE) signal at 1.85 GHz with a 10-MHz bandwidth and a 16-QAM 7.5 dB PAPR, the CMOS envelope tracking (ET) PA module achieves a power-added efficiency (PAE) of 35.4%, an error vector magnitude (EVM) of 3.6%, and an ACLR_E-UTRA of -33.3 dBc at an average output power of 26.5 dBm. The ET PA with the control circuits improves the gain deviation within 2 dB and the PAE up to 5%, respectively, according to the output power level, over those of the ET PA without the dynamic control for the same LTE signal.