A Physically Based Scalable SPICE Model for High-Voltage Super-Junction MOSFETs

This paper proposes a novel physical scalable SPICE model for Super Junction MOSFETs. The model is based on technology process and layout parameters, enabling a direct link between SPICE and process development. One model covers all device sizes and process perturbations. Designers have the ability to optimize a device in a given technology for achieving optimum performance over device size. Further, designers can use the model to predict new technology performance through variation and optimization of the process parameters.