Effect of temperature and chiral vector on emerging CNTFET device

In this paper we have analyzed the merits of CNTFET devices over MOSFET in nanoscale regime, by comparing the effect of oxide thickness on quantum capacitance. After this we have observed and analyzed the effect of variation of chiral vector and temperature on threshold voltage of CNTFET device. After simulation on HSPICE tool we can conclude that for high threshold voltage as required for low leakage in nanoscaled devices, chiral vector (m,n) should be relatively small. We have further analyzed the effect of temperature on threshold voltage in CNTFET devices and is found to be negligibly small. There is a little variation in the threshold voltage for both positive and negative temperatures.