Design of low power split path Data Driven Dynamic ripple carry adders

Addition is the fundamental operation used in computer arithmetic circuits and CMOS adder is the basic component of these systems. This paper presents the designs of new 4-bit and 8-bit split-path Data Driven Dynamic logic (sp-D3L) ripple carry adder (RCA) circuit. Power consumption of proposed 4-bit RCA's varies from 0.69nW to 2.75nW with variation in supply voltage from 1.8V to 3.3V. Maximum output delay shows variation from 55.42ps to 245.98ps. Power consumption of proposed 8-bit RCA's varies from 1.37nW to 5.52nW with variation in supply voltage from 1.8V to 3.3V. Maximum output delay shows variation from 54.96ps to 246.25ps. Simulations have been performed using SPICE based on TSMC 0.18µm CMOS technology. Power consumption and delay of proposed RCA adder circuit have been compared with earlier reported circuits and proposed circuit shows better performance.