On the FPGA board level routing problem

We study a two-terminal board level routing problem applicable to FPGA-based logic emulation systems. The problem was studied by W. Mak and D.F. Wong (see IEEE Trans. CAD, vol.16, no.3, 1997), where an algorithm of O(n/sup 2/) time was proposed, where n is the number of nets. We present a new and simple O(n)-time routing algorithm for solving the problem. A new precise I/O capacity constraint for routability is given by taking other criteria (e.g., the number of chips) into consideration.