A pipelined systolic architecture for a Kalman-filter-based signal reconstruction algorithm

This paper examines the application of the pipeline technique to a systolic architecture called SYSKAL, which is dedicated to a Kalman-filter-based algorithm for signal reconstruction. The delay of the multipliers and adders limits the performance of this architecture. In this paper, we show that the particularity of the data flow of the algorithm and of the systolic design make possible a deep pipelined version of the architecture. The pipeline technique is applied in three steps, three architecture versions are proposed and evaluated. A reduction of the number of multipliers allows us to conserve the same design area as that of a non-pipeline technique. The throughput is then improved without change to the area. A comparative study of performance is done in terms of computational time and area for each version and for the Motorola's general-purpose DSP56001 digital signal processor.