Design of 60-GHz 90-nm CMOS balanced power amplifier with miniaturized quadrature hybrids

This paper presents a 60-GHz CMOS balanced power amplifier (PA) with miniaturized quadrature hybrids using 90-nm CMOS technology. To improve the output power and provide an area-efficient solution for the balanced PA design, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme is employed as a low-insertion-loss power splitter/combiner. With a very short effective guided wavelength of 0.072 λ
_g
, the simulated insertion loss and phase difference of the quadrature hybrids are better than 0.5 dB and 90° ± 0.2°, respectively. The designed PA reaches a power gain exceeding 13.2 dB and a saturation power of 10.7 dBm with a power-added efficiency (PAE) more than 9 % at 60 GHz. The power consumption of the PA is 109 mW at a 1.2 V supply voltage. The chip size is 0.68 mm
²
.