A low power FIR filter structure based on a modified distributed arithmetic algorithm

FIR digital filter is an important part in modern signal processing system. With the increase of arithmetic speed, reducing the occupation of resources or power consumption is an effective method to improve the performance of the whole system. This paper proposes a novel finite impulse response filter structure based on the modified distributed arithmetic (MDA) method. We first reduce the redundant coefficient items to save the chip area and power. Then, four FIR filters with different orders are implemented respectively using the proposed method (proposed method). The experimental results show that, comparing to the published method (published method), the proposed method can save chip area up to 17.4%, while the power reduction up to 13.0%.