High speed low power DWT structure with log based FPU in FPGAs

Wavelet transforms have become one of the basic tools of signal and image processing, digital communications and other applications. Biorthogonal wavelet transform attains further more importance as it allows the construction of symmetric wavelet, which provides the linear phase filter. As the lossy biorthogonal 9/7 (B9/7) transform uses floating point lifting coefficients, the computational complexity of the overall structure gets increased as the levels are increased. This leads to unwanted increment in additional latency in the overall circuit and also hardware realization leads to increased area and power consumption. Hence in this paper, we propose an alternate structure for arithmetic computations involved in the B9/7 DWT which utilizes the power saving attribute of Logarithmic Number Systems (LNS). This LNS adaptation in arithmetic unit results in overall accuracy enhancement with reduced area and power consumption. We also explored the constituent latency and found that the main memory access for the input feed is one of the main factors that increase the latency in the circuit. Hence, we attain a feasible solution of segregating the main memory from the structure, and inputs are fed from temporary memory blocks to the structure. Hence, symmetric extension of the image to be transformed is handled in a way that does not require additional computation or clock cycles; it is expected to provide a reduction in hardware complexity and increase in computational speed. We evaluated the performance and correctness of the architecture by implementing in Xilinx Virtex 6 field programmable gate arrays.