Implementation of extended Open Core Protocol interface memory system using Verilog HDL

In today's Soc design, a large number of Intellectual Property(IP) are incorporated and their complexity keeps increasing depending upon the application. Hence for communication between these IP cores, a standard communication protocol for all the IP entities in the IC is developed, the Open Core Protocol(OCP), instead of communicating for each set of IP cores. Open Core Protocol (OCP) achieves the goal of IP design reuse and meets shorter time to market requirements when compared to the standard bus interfaces. OCP comes under the class of Socket based interface standard. This paper mainly focuses on the design and implementation of a memory interfacing system using Extended OCP signals along with burst support. The design mainly includes Processor as master and RAM as slave. Here we perform the communication (simple read and write operations) between the two entities using OCP architecture with various modes burst support and the newly added set of signals from the class of simple extensions and dataflow signals. The main advantage of adding these signals is to ensure the correctness of send and receive data because our aim is to make the communication protocol secure and efficient. Also the importance of read/write command extension Read Exclusive operation is implemented. The proposed design is implemented in Verilog HDL and synthesis is done using Xilinx ISE Design Suite 12.1. Finally power calculations were taken using Xilinx Xpower Analyser.