Design of a time-slot-interchanger and other TDM bus interfacing issues

This paper shows the design for an inexpensive time-slot-interchanger (TSI) for interchanging time-slot data between several time-division-multiplexed (TDM) busses. Additionally, many TDM bus-interfacing problems are discussed and solutions presented. The example TSI, design interfaces eight T1/E1 lines, although it is expandable in both the number of lines and speed. Routing of time-slot-data is done through a routing table stored in SRAM. It allows the data from one time slot to be routed to another time-slot on the same or different TDM bus. The TSI also has features that allow for the control of external buffers and non-TDM capable chips. It also allows for the generation of auxiliary frame sync signals for those difficult to interface chips. The TSI logic can be implemented in a <10K gate FPGA and small external Sync-SRAM- for a very low cost solution.