Specifications for a multi-standard SBCD/ARGOS-3 integrated UHF satellite receiver

The specifications for the front-end design of a SBCD/ARGOS-3 integrated UHF receiver in a 0.13 μm star-dard CMOS process are derived. A low intermediate frequency architecture is presented, in which a 3-stage low-noise amplifier, a passive mixer and a phase-locked loop based frequency synthesizer are employed for achieving the resulting specs.