Ultra-low noise and high PSR LDO design

This paper presents a new ultra-low noise and high PSR LDO structure. This structure can achieve ultra-low noise performance without large filter capacitor by incorporating a capacitance amplifying circuit in the structure of LDO with pre-regulation. A large amount of chip area will be saved in this structure. Also this structure can achieve high PSR under a wide frequency range by introducing a feed-forward path between the drain and gate of the pass transistor. A novel LDO in proposed structure is realized under SMIC 0.18µm process. The experimental results show that proposed LDO structure can achieve a total output noise of 25.5µV between 10Hz–1KHz and 56.4µV between 1KHz-1MHz with a filter capacitor of 5pF. PSR is −71.6dB under low frequency until 49KHz and at least −65.7dB under entire frequency range.