An area-efficient implementation of ΣΔ ADC multistage decimation filter

In this paper, an area-efficient implementation of a multistage decimation filter for audio ΣΔ ADC is presented. The decimator with a decimation ratio of 256 has less than 0.005dB passband ripple and 100dB stop band attenuation. It has an audio passband of 0–20kHz and outputs 16-bit resolution signal at 48kHz. With an area-efficient architecture involving RAM and ROM, and the dedicated instruction scheduling through 256 steps in a cycle, the decimator is synthesized with fewer than 300 LUTs and fewer than 160 Slices on a Xilinx Spartan3E FPGA. An ALU with only one 32-bit processing register and one 16-bit output register is designed. The computing rate or the clock rate is equal to the input sampling rate, which lowers power consumption and simplifies clock generation design. A Matlab compiler is developed to automate the generation of ROM word bits according to the instruction scheduling. At last, the simulation result of the RTL model in Modelsim is verified by the Matlab\Simulink programs to ensure that the internal 32-bit register data is ‘bit true’ while processing the 1-bit input stream.