Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier

A new time-interleaved band-pass ΣΔ modulator architecture targeted for Class-S power amplifier is presented. To demonstrate the feasibility a 10th order 60MHz bandwidth modulator based on this architecture is designed in a standard 65nm CMOS process. 54dB of signal noise ratio (SNR) is gotten at a sample rate of 1.92GHz through simulation.