Repeater insertion to reduce delay and power in RC tree structures

In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The proper insertion of repeaters alleviates the quadratic increase in propagation delay with the interconnect length while decreasing the power dissipation by reducing the short-circuit current. These repeaters are inserted within different types of common resistive interconnect structures, such as a line or a tree. The application of repeaters to RC tree structures is discussed. A tree topology is a common interconnect structure frequently found in VLSI circuits. A short-channel transistor model is used as a foundation for the development of delay and power expressions to develop a design methodology for inserting repeaters into an RC tree network. Power dissipation expressions for these repeater structures are presented which consider both dynamic and short-circuit power. These design expressions are validated against simulated experiments with a maximum 11% and 16% deviation from SPICE for delay and power, respectively.