Reliable ALU design with optimized voltage and implementation on 28nm FPGA

In this work 40nm Virtex-6 and 28nm Artix7 is target Device. Xilinx 14.2 ISE is a Design tool, ALU is target Design. In this work, we apply voltage optimization to reduce dynamic power in both 28nm and 40nm technologies. With the help of voltage optimization, there is 93.74%, 93.64%, 93.52%, 93.51% and 93.54% reduction in power on 28nm for range of 1V-0.5V with step size of 0.1V on 100 MHz in comparison to power consumption on 40nm. There is 90.65%, 90.04%, 89.48%, 89.13% 88.99 and 88.88% reduction in power on for range of 1V-0.5V with step size of 0.1V on 1 GHz in comparison to 40nm technology FPGA. There is 69.39 %, 66.78%, 64.81%, 63.38%, 62.47% and 61.92% reduction in power on 28nm technology for range of 1V-0.5V with step size of 0.1V on 10 GHz. 32.86 %, 30.77%, 29.24%, 28.10%, 27.25% and 26.57% power reduction is possible on 28nm technology for range of 1V-0.5V with step size of 0.1V on 100 GHz. If device operating frequency is 1 THz, then 19.28%, 19.05%, 18.79%, 18.48%, 18.14% and 17.74% reduction in power on 28nm technology is possible for range of 1V-0.5V with step size of 0.1V on in comparison to power consumption of 40nm technology. 28nm Technology based FPGA is more power effective FPGA in comparison to 40nm technology based FPGA. On 100 MHz, power reduction is maximum i.e. 93.74%. On 1 THz, it is minimum i.e. 19.28%. Voltage Scaling is able to reduce total power consumption in range of 93.74%-19.28%.