A new test structure to characterize the latchup effect

A test structure for easily determining the sensitivity of different geometries and technological options to latchup is presented. The circuit is an astable oscillator composed of a p-n-p-n device with an integrated resistor and capacitor. It is used to obtain fast and comparative results with very simple instrumentation. Test structures are designed and produced with a 5- mu m CMOS process, although they are specially suited for VLSI technologies. Experimental results give very good agreement with other latchup test procedures. Much more accuracy can be obtained with a simple digital oscilloscope.<>